Power Integrity Analysis

On the high-speed design, analysis and verification techniques early in the design cycle, designers can eliminate layout iterations and ensure that products are marketed on time.

Obtaining impedance profiles of the power system network, analysis in the frequency domain (noise at various frequencies and resonant behaviour), analysis in the time domain (noise at various points of time) and different isolation studies needs to be performed. A good decoupling design, studies need to be done on capacitor placement and selection (dielectric types, body sizes and values), via placement, capacitor landing pad design, ferrite bead selection and design,analysis of power islands / power splits.

The designs often require more power to travel across a limited amount of space; several factors still affect the density of a design and how much power it can actually handle. There are many variables include the amount of space that is actually available height, width and length, thickness and number of copper layers in the printed circuit board and how the flow pattern influence the interconnect temperature rise. These elements needs to be carefully studied and good understanding each of these in the early design phase is necessary to successfully design power integrity into the system and speed up the design process.

Next is the integrity, or absence of noise of the delivered power. The designer needs to determine the number and location of decoupling capacitors and the goal is to save component cost and board area by avoiding over-conservative (excessive) use of bypass capacitors. The designer may also want to experiment with the PCB fabrication materials and stack-up to determine the best electrical and cost solution.

Medontech can analyse and optimize board design to identify potential power integrity problems.